The decoder system of digital TV broadcast receiver used on a movable platform, such as a car navigation system, requires a tuner and Motion Picture Expert's Group (MPEG) decoder pair for each bitstream of HDTV (12-segment) and QVGA (1-segment), independently. This requirement remains even though only one of inputs is selected as source of displayed images. Providing two such tuner/MPEG decoder pairs consumes a disadvantageous amount of electric power and makes the decoder system large.
It is feasible in the current art to watch digital TV broadcast programs on movable platforms such as commercial car navigation systems, mobile PCs or mobile phones. In car navigation systems watching HDTV (12-segment) broadcasting of VGA sized display is feasible. While watching TV on such a car navigation system, motion of the car changes the received TV signal. Sometimes the TV receiver can no longer receive the TV signal correctly. For example, the receiver may not be able to receive the TV signal correctly near mountains or within tunnels.
In such case, the receiver stops decoding the HDTV (12-segment) broadcast and switches to decoding the QVGA (1-segment) broadcast. Contents of both transmissions are the same. However, the mass of information (such as image size, sound quality, frame rate and etc) are much differently coded.
FIG. 1 illustrates a block diagram of this prior art receiver 100. First antenna 111 receives the 12-segment HDTV broadcast and supplies the received signal to tuner 112. Tuner 112 detects the HDTV broadcast signal and supplies a bitstream to first MPEG decoder 113. Tuner 112 also produces a receiver status signal 114. Receiver status signal 114 is a digital signal indicating the receiver status as good or bad. MPEG decoder 113 employs a number of frame buffers 115. These are preferably stored in synchronous dynamic random access memory (SDRAM). As known in the art MPEG decoding often includes differential coding from a prior frame or a following frame requiring storing data for decoding. MPEG decoder 113 generates decoded HDTV images supplied to a first input of multiplexer 120. These HDTV images are used as references for other decoding. FIG. 1 illustrates a connection from the decoded image output of MPEG decoder 113 to frame buffers 115. This provides a path for decoded HDTV images to be stored in frame buffers 115. MPEG decoder 113 uses the image data stored in frame buffers 115 in decoding. Note that frame buffers 115 store HDTV size images.
Second antenna 131 receives the 1-segment QVGA broadcast and supplies the received signal to tuner 132. Tuner 132 detects the QVGA broadcast signal and supplies a bitstream to second MPEG decoder 113. MPEG decoder 133 employs a number of frame buffers 134. These are preferably stored in SDRAM. MPEG decoder 133 generates decoded QVGA images supplied to a second input of multiplexer 120. FIG. 1 illustrates a connection from the decoded image output of MPEG decoder 133 to frame buffers 134. This provides a path for decoded QVGA images to be stored in frame buffers 134. MPEG decoder 133 uses the image data stored in frame buffers 134 in decoding. Note that frame buffers 134 store QVGA sized images.
Multiplexer 120 selects between the decoded HDTV image signal from MPEG decoder 113 and the decoded QVGA image signal from MPEG decoder 133 based upon receiver status signal 114. If receiver status signal 114 indicates that the HDTV receiver status is good, then multiplexer 120 selects the HDTV image signal. If receiver status signal 114 indicates that the HDTV receiver status is bad, then multiplexer 120 selects the QVGA image signal. The signal selected by multiplexer 120 supplies resize circuit 121. Resize circuit 121 resizes the received signal to an appropriate size for display 122. Note the impute image may be a HDTV image or a QVGA image according to the selection of multiplexer 120. In the preferred embodiment the resized signal is a VGA signal (800 horizontal dots in 480 lines) and display 122 is a VGA display.
This system requires two pairs of tuner/decoder pairs of circuits. These are: first pair tuner 112 and MPEG decoder 113; and second pair tuner 133 and MPEG decoder 133. Each tuner/decoder pair work concurrently and continuously during period when the DTV decoder system is activated. This is required even though only one pair is selected by multiplexer 120 to produce the displayed image and other pair is not used. Employing two such tuner/MPEG decoder pairs consumes a disadvantageous amount of electric power and makes the decoder system large.